Reducing Energy Consumption for Instruction Fetch on

Embedded Processors

Professor Gary Tyson

Computer Science Department

Florida State University

Tallahasse, FL

Abstract

In this talk I will present two power savings enhancements designed to reduce the cost of instruction fetch on embedded processors.  The first technique, the Tagless Hit Instruction Cache (THIC),  avoids the performance associated with very small instruction caches misses by determining when the cache will not miss and bypassing when the guarantee cannot be made. The second technique reduces required instruction fetch cache references by creating an Instruction Register File (IRF) to hold common instructions. Together these techniques can reduce power consumption for low power embedded processors by as much as 40%. We are currently working to commercialize each design and  I will discuss the difficulties we have encountered in extending academic research into commercial products.

Speaker’s Biographical Sketch

Gary Tyson is an Associate Professor in the Computer Science Department at Florida State University.  Professor Tyson received his PhD in 1997 from the University of California - Davis.  He was on the faculty at the University of California - Riverside  and the University of Michigan before joining FSU in 2003. His research is in computer architecture and embedded systems, involving the design of low power processors. 

DATE: Wednesday, January 30, 2008

TIME: 12:00 – 1:00 PM

LOCATION: 424 Benedum Hall