University of Pittsburgh

Fall  2008 Course Offering

This course will present an introduction to the design and analysis of digital Very Large Scale Integration (VLSI) technology using state-of-the-art computer aided design (CAD) tools.   
 

Note: with this offering we are changing many things: the text, the Unix workstations, and the CAD software. While much of the previous year's notes are valid, many details will be different.

2008 Syllabus

2008 Revised Course Schedule

 

2008 Lecture Material (using Weste and Harris):

• Lecture 0

• Lecture 1
• Lecture 1A

• Lecture 2

• Lecture 3

• Lecture 4 (Note: Also see Chapter 5 from 2006)

• Lecture 7 (Spice Notes)

• Lecture 5 (Note:  Also see Chapter 6 from 2006)
• Lecture 6
• Lecture 8
• Lecture 9
• Lecture 10
• Lecture 11
• Lecture 12
• Lecture 13
• Lecture 14
• Lecture 20
• Lecture 21

2008 Laboratory Material:

• Lab 1
• Lab 2
• Lab 3
• Lab 4
• Lab 5
• Lab 6
• Lab 7
• Lab 8
• Lab 9
• Lab 10

Related Links:

• VLSI Educational Tools at Penn State

• Microsystems Prototyping Laboratory at Mississippi State

• University of Texas Adnan Aziz VLSI Class

• Micro Magic, Inc. Home Page

• UMC Fabrication

• Design And Reuse, IP, Core, System-On-Chip

• TimberWolf Place and Route

• SPICE 3 Overview

• Spice32

• Poly FET parameter Files

Tutorials:

• Pitt Tutorial 1: Virtuoso 6.1.2 Analog Artist with Spectre and the 1.6 (beta) CDK from NCSU

• Pitt Tutorial 2: Generating Transistor I-V Curves with Spectre

• Pitt Tutorial 3: Runing Spice/Spectre directly

• Pitt Tutorial 4: Virtuoso XL Layout

• Pitt Tutorial 4A: Using Piecewise Linear Files for Testing

• Pitt Tutorial 5: Synthesis with Synopsys Design Compiler and Cadence Encounter

• Pitt Tutorial 6: Simulation with Modelsim

• Pitt Tutorial 7: Layout Generation and Extraction Notes for NCSU/OSU 45nm FreePDK

• NCSU VLSI Wiki

• http://www.ee.virginia.edu/~mrs8n/cadence/Cadencetutorials.html

• http://vlsi.olin.edu/vlsiwiki/CadenceTutorial

• http://www.vlsi.wpi.edu/cds/

• http://www.seas.upenn.edu/~eecad/cadence/cadence.html

• http://www.cse.sc.edu/~jbakos/613/index.shtml

• http://bwrc.eecs.berkeley.edu/Classes/Icdesign/ee141_f03/CadenceLabs/Lab2/VirtuosoTutorial.htm
  

2006 Lecture Material (using Rabaey's Book):

• Chapter 1: Introduction
• Chapter 2: CMOS Manufacturing
• Chapter 3: MOS devices    NEW SLIDES
• Chapter 4: The Wire
• Chapter 5: The Inverter
• Chapter 6: Combinational Logic
•     West and Harris Combinational Circuit Chapter
• Chapter 7: Sequential Logic
• Chapter 8: Design Methodologies
• Chapter 10: System Timing
• Chapter 11: Arithmetic Circuits
• Chapter 12: Memories

2006 Lab Material (Max and Sue):

• Lab 1: Getting Started on Unix Machines
• Lab 2: Simulation with HSPICE
• Lab 3: MOS Simulations with HSPICE
• Lab 4: Sue and Max and HSPICE
• Lab 5: Delays
• Lab 6: Standard Cells
• Lab 7: IRSIM
• Lab 8: Data Path Compiler
• Lab 9: Hierarchy with DPC
 


 
 

03/24/09