So you want to make an actual design using the hardware reference board? This document attempts to assist you in that goal, by providing the signal to pin mapping implemented in the printed circuit board. *** Quartus and Pin Assignments *** Quartus stores pin assigments in a file of the form .csf, in the CHIP section. For example, a typical csf file might contain: CHIP(top_level_project_name) { ext_flash_cs_n : LOCATION = Pin_E1; ext_flash_we_n : LOCATION = Pin_H13; } LOCATION directives can be added to the csf file with any text editor, but be sure to close Quartus first! (Quartus does not suspect that anyone would ever edit the csf file, and so will overwrite all of your changes at random times.) Two sections of information follow: *** Basic Infrastructure Signals *** Just about any Nios design will require these signals. Copy and paste the following lines into your csf file (omitting comment and blank lines), and then double-check your signal names against the ones used here. (A common mistake is to rename a signal (by changing the properties of an I/O pin, for example), leading to a mismatch between the LOCATION signal and the actual signals of the design.) clk : LOCATION = Pin_L6; # Byte enables for offchip memory. off_chip_shared_be_n[0] : LOCATION = Pin_F5; off_chip_shared_be_n[1] : LOCATION = Pin_F2; off_chip_shared_be_n[2] : LOCATION = Pin_F4; off_chip_shared_be_n[3] : LOCATION = Pin_H5; # Off-chip address signal. off_chip_shared_address[0] : LOCATION = Pin_G17; off_chip_shared_address[10] : LOCATION = Pin_A3; off_chip_shared_address[11] : LOCATION = Pin_A4; off_chip_shared_address[12] : LOCATION = Pin_C3; off_chip_shared_address[13] : LOCATION = Pin_C1; off_chip_shared_address[14] : LOCATION = Pin_D3; off_chip_shared_address[15] : LOCATION = Pin_D2; off_chip_shared_address[16] : LOCATION = Pin_C2; off_chip_shared_address[17] : LOCATION = Pin_F3; off_chip_shared_address[18] : LOCATION = Pin_B3; off_chip_shared_address[19] : LOCATION = Pin_E3; off_chip_shared_address[1] : LOCATION = Pin_A8; off_chip_shared_address[2] : LOCATION = Pin_B8; off_chip_shared_address[3] : LOCATION = Pin_A7; off_chip_shared_address[4] : LOCATION = Pin_B7; off_chip_shared_address[5] : LOCATION = Pin_B6; off_chip_shared_address[6] : LOCATION = Pin_A6; off_chip_shared_address[7] : LOCATION = Pin_A5; off_chip_shared_address[8] : LOCATION = Pin_B5; off_chip_shared_address[9] : LOCATION = Pin_B4; # Off-chip data. off_chip_shared_data[0] : LOCATION = Pin_C4; off_chip_shared_data[10] : LOCATION = Pin_C5; off_chip_shared_data[11] : LOCATION = Pin_D6; off_chip_shared_data[12] : LOCATION = Pin_C6; off_chip_shared_data[13] : LOCATION = Pin_F9; off_chip_shared_data[14] : LOCATION = Pin_H10; off_chip_shared_data[15] : LOCATION = Pin_D7; off_chip_shared_data[16] : LOCATION = Pin_C7; off_chip_shared_data[17] : LOCATION = Pin_E9; off_chip_shared_data[18] : LOCATION = Pin_E10; off_chip_shared_data[19] : LOCATION = Pin_D9; off_chip_shared_data[1] : LOCATION = Pin_H11; off_chip_shared_data[20] : LOCATION = Pin_C8; off_chip_shared_data[21] : LOCATION = Pin_F10; off_chip_shared_data[22] : LOCATION = Pin_G11; off_chip_shared_data[23] : LOCATION = Pin_C9; off_chip_shared_data[24] : LOCATION = Pin_C10; off_chip_shared_data[25] : LOCATION = Pin_H12; off_chip_shared_data[26] : LOCATION = Pin_D10; off_chip_shared_data[27] : LOCATION = Pin_G12; off_chip_shared_data[28] : LOCATION = Pin_G13; off_chip_shared_data[29] : LOCATION = Pin_F11; off_chip_shared_data[2] : LOCATION = Pin_G10; off_chip_shared_data[30] : LOCATION = Pin_B11; off_chip_shared_data[31] : LOCATION = Pin_B10; off_chip_shared_data[3] : LOCATION = Pin_D8; off_chip_shared_data[4] : LOCATION = Pin_E7; off_chip_shared_data[5] : LOCATION = Pin_D4; off_chip_shared_data[6] : LOCATION = Pin_D5; off_chip_shared_data[7] : LOCATION = Pin_G9; off_chip_shared_data[8] : LOCATION = Pin_F8; off_chip_shared_data[9] : LOCATION = Pin_E8; # Flash memory chip select and write-enable. ext_flash_cs_n : LOCATION = Pin_E1; ext_flash_we_n : LOCATION = Pin_H13; # Shared off-chip output enable (goes to flash and SRAM). off_chip_shared_oe_n : LOCATION = Pin_A2; # Address 17 to the SRAM (drive it with off_chip_shared_be_n[17]). ext_sram_addr17 : LOCATION = Pin_D1; # SRAM write enable ext_sram_we_n : LOCATION = Pin_E6; # An output of the 7064 part. Configure as an input. flash_byte_n : LOCATION = Pin_V5; # System reset. reset_n : LOCATION = Pin_F12; # 12 bits of in_port_to_the_button data. in_port_to_the_button[0] : LOCATION = Pin_Y9; in_port_to_the_button[10] : LOCATION = Pin_U12; in_port_to_the_button[11] : LOCATION = Pin_Y10; in_port_to_the_button[1] : LOCATION = Pin_T9; in_port_to_the_button[2] : LOCATION = Pin_Y8; in_port_to_the_button[3] : LOCATION = Pin_W9; in_port_to_the_button[4] : LOCATION = Pin_V9; in_port_to_the_button[5] : LOCATION = Pin_U9; in_port_to_the_button[6] : LOCATION = Pin_T10; in_port_to_the_button[7] : LOCATION = Pin_U10; in_port_to_the_button[8] : LOCATION = Pin_V10; in_port_to_the_button[9] : LOCATION = Pin_P11; # Two yellow out_port_from_the_leds. out_port_from_the_led[0] : LOCATION = Pin_T18; out_port_from_the_led[1] : LOCATION = Pin_T19; # The seven-segment out_port_from_the_led. out_port_From_the_seven_segment[0] : LOCATION = Pin_W17; out_port_From_the_seven_segment[10] : LOCATION = Pin_Y17; out_port_From_the_seven_segment[11] : LOCATION = Pin_V8; out_port_From_the_seven_segment[12] : LOCATION = Pin_Y7; out_port_From_the_seven_segment[13] : LOCATION = Pin_U11; out_port_From_the_seven_segment[14] : LOCATION = Pin_R11; out_port_From_the_seven_segment[15] : LOCATION = Pin_D18; out_port_From_the_seven_segment[1] : LOCATION = Pin_U18; out_port_From_the_seven_segment[2] : LOCATION = Pin_Y18; out_port_From_the_seven_segment[3] : LOCATION = Pin_W18; out_port_From_the_seven_segment[4] : LOCATION = Pin_U8; out_port_From_the_seven_segment[5] : LOCATION = Pin_T11; out_port_From_the_seven_segment[6] : LOCATION = Pin_R10; out_port_From_the_seven_segment[7] : LOCATION = Pin_C18; out_port_From_the_seven_segment[8] : LOCATION = Pin_V17; out_port_From_the_seven_segment[9] : LOCATION = Pin_V18; # Serial port bits (from the Apex's perspective; rxd is an input). rxd_to_the_uart0 : LOCATION = Pin_W8; txd_from_the_uart0 : LOCATION = Pin_D15; # Paired SRAM chip selects. select_0_n_to_the_ext_ram : LOCATION = Pin_E4; select_1_n_to_the_ext_ram : LOCATION = Pin_E2; # A reserved signal into the 7064. Drive with GND, unless you need to # reconfigure your Apex under Apex control (yikes!). See the 7064 source # for more details.. apex_reload_n : LOCATION = Pin_C19; # Optional rx and tx for a second UART (e.g. for GDB use): # (See GDB app note.) rxdGDB : LOCATION = Pin_F14; txdGDB : LOCATION = Pin_F13; *** Connections to various connectors on the board: *** The following is a list of Apex pins, schematic signals and connector designators. The data herein can be converted into LOCATION designations for inclusion in the csf file. It's impossible to anticpate your chosen signals for these pins and connectors, so a bit more editing is necessary here before this data can be dropped into a csf file. *** Important note: *** During board test, certain signals were implicated with causing internal errors during Quartus compile. This issue is in the process of being resolved. In the meanwhile, if possible, avoid using any signals with the comment "Unresolved issue" attached to them. # Protocard connector (JP8, JP9, JP10): N20 proto_card_1[0] JP8-3 K20 proto_card_1[1] JP8-4 P4 proto_card_1[2] JP8-5 K4 proto_card_1[3] JP8-6 # Unresolved issue: including the following pin in a design may lead to # a Quartus internal error during compilation. V11 proto_card_1[4] JP8-7 K22 proto_card_1[5] JP8-8 K19 proto_card_1[6] JP8-9 P22 proto_card_1[7] JP8-10 N22 proto_card_1[8] JP8-11 R22 proto_card_1[9] JP8-12 # Unresolved issue: including the following pin in a design may lead to # a Quartus internal error during compilation. V12 proto_card_1[10] JP8-13 # Unresolved issue: including the following pin in a design may lead to # a Quartus internal error during compilation. K17 proto_card_1_clk2 JP10-13 N5 proto_card_1[11] JP8-14 L7 proto_card_1[12] JP8-15 # Unresolved issue: when the following pin is driven, the board # crashes/reconfigures/is unhappy. N21 proto_card_1[13] JP8-16 P21 proto_card_1[14] JP8-17 K16 proto_card_1[15] JP8-18 P20 proto_card_1[16] JP8-21 K15 proto_card_1[17] JP8-23 R5 proto_card_1[18] JP8-25 V6 proto_card_1_sel JP8-38 N6 proto_card_1[19] JP8-27 L20 proto_card_1[20] JP8-28 J18 proto_card_1[21] JP8-29 K18 proto_card_1[22] JP8-31 M17 proto_card_1[23] JP8-32 J3 proto_card_1[24] JP8-33 K5 proto_card_1[25] JP8-35 R4 proto_card_1[26] JP8-36 J7 proto_card_1[27] JP8-37 J5 proto_card_1[28] JP8-39 N18 proto_card_1[29] JP9-4 M20 proto_card_1[30] JP9-5 L16 proto_card_1[31] JP9-6 R21 proto_card_1[32] JP9-7 L17 proto_card_1[33] JP9-8 K3 proto_card_1[34] JP9-9 N2 proto_card_1[35] JP9-10 J1 proto_card_1[36] JP9-11 J2 proto_card_1[37] JP9-12 M6 proto_card_1[38] JP9-13 M16 proto_card_1[39] JP9-14 # Protocard connector (JP11 JP12, JP13): L15 proto_card_2[0] JP11-3 P19 proto_card_2[1] JP11-4 N19 proto_card_2[2] JP11-5 R20 proto_card_2[3] JP11-6 M3 proto_card_2[4] JP11-7 N1 proto_card_2[5] JP11-8 U5 proto_card_2[6] JP11-9 M2 proto_card_2[7] JP11-10 K1 proto_card_2[8] JP11-11 T22 proto_card_2[9] JP11-12 L14 proto_card_2[10] JP11-13 T20 proto_card_2[11] JP11-14 N17 proto_card_2[12] JP11-15 # Unresolved issue: when the following pin is driven, the board # crashes/reconfigures/is unhappy. T21 proto_card_2[13] JP11-16 R3 proto_card_2[14] JP11-17 P1 proto_card_2[15] JP11-18 P3 proto_card_2[16] JP11-21 N3 proto_card_2[17] JP11-23 K2 proto_card_2[18] JP11-25 V7 proto_card_2_sel JP11-38 # Unresolved issue: including the following pin in a design may lead to # a Quartus internal error during compilation. M18 proto_card_2_clk2 PCARD2_0_pi[19] JP13-13 R19 proto_card_2[19] JP11-27 M15 proto_card_2[20] JP11-28 N16 proto_card_2[21] JP11-29 U22 proto_card_2[22] JP11-31 P18 proto_card_2[23] JP11-32 U3 proto_card_2[24] JP11-33 T1 proto_card_2[25] JP11-35 R1 proto_card_2[26] JP11-36 R2 proto_card_2[27] JP11-37 P2 proto_card_2[28] JP11-39 W20 proto_card_2[29] JP12-4 R18 proto_card_2[30] JP12-5 N15 proto_card_2[31] JP12-6 U21 proto_card_2[32] JP12-7 P17 proto_card_2[33] JP12-8 U1 proto_card_2[34] JP12-9 U2 proto_card_2[35] JP12-10 T2 proto_card_2[36] JP12-11 T3 proto_card_2[37] JP12-12 U4 proto_card_2[38] JP12-13 U19 proto_card_2[39] JP12-14 # PMC Mezzanine connector (JN1, JN2): B12 pmc_connector[0] JN1-4 B13 pmc_connector[1] JN1-5 B14 pmc_connector[2] JN1-6 A15 pmc_connector[3] JN1-7 B15 pmc_connector[4] JN1-9 A16 pmc_connector[5] JN1-10 B16 pmc_connector[6] JN1-12 A17 pmc_connector[7] JN1-16 B17 pmc_connector[8] JN1-17 A18 pmc_connector[9] JN1-20 B18 pmc_connector[10] JN1-21 A19 pmc_connector[11] JN1-22 B19 pmc_connector[12] JN1-23 A20 pmc_connector[13] JN1-26 D21 pmc_connector[14] JN1-27 E21 pmc_connector[15] JN1-28 A21 pmc_connector[16] JN1-29 # Unresolved issue: when the following pin is driven, the board # crashes/reconfigures/is unhappy. F21 pmc_connector[17] JN1-32 C22 pmc_connector[18] JN1-33 C12 pmc_connector[19] JN1-36 D22 pmc_connector[20] JN1-37 B20 pmc_connector[21] JN1-38 C21 pmc_connector[22] JN1-40 C20 pmc_connector[23] JN1-41 D19 pmc_connector[24] JN1-42 C13 pmc_connector[25] JN1-43 E18 pmc_connector[26] JN1-46 D20 pmc_connector[27] JN1-47 G19 pmc_connector[28] JN1-48 E19 pmc_connector[29] JN1-49 F19 pmc_connector[30] JN1-52 E5 pmc_connector[31] JN1-53 M7 pmc_connector[32] JN1-54 E22 pmc_connector[33] JN1-55 G20 pmc_connector[34] JN1-58 F20 pmc_connector[35] JN1-59 F18 pmc_connector[36] JN1-60 E20 pmc_connector[37] JN1-61 G3 pmc_connector[38] JN1-64 F7 pmc_connector[39] JN2-8 G6 pmc_connector[40] JN2-9 G18 pmc_connector[41] JN2-10 H17 pmc_connector[42] JN2-11 F22 pmc_connector[43] JN2-14 H22 pmc_connector[44] JN2-16 H20 pmc_connector[45] JN2-17 F1 pmc_connector[46] JN2-19 H1 pmc_connector[47] JN2-20 L8 pmc_connector[48] JN2-22 G2 pmc_connector[49] JN2-23 H3 pmc_connector[50] JN2-25 H18 pmc_connector[51] JN2-26 H21 pmc_connector[52] JN2-28 H19 pmc_connector[53] JN2-29 G22 pmc_connector[54] JN2-31 J16 pmc_connector[55] JN2-32 G4 pmc_connector[56] JN2-34 J4 pmc_connector[57] JN2-35 K7 pmc_connector[58] JN2-38 G5 pmc_connector[59] JN2-39 G1 pmc_connector[60] JN2-42 J17 pmc_connector[61] JN2-43 G21 pmc_connector[62] JN2-45 L21 pmc_connector[63] JN2-46 B9 pmc_connector[64] JN2-48 J21 pmc_connector[65] JN2-49 J22 pmc_connector[66] JN2-51 H6 pmc_connector[67] JN2-52 H4 pmc_connector[68] JN2-54 H2 pmc_connector[69] JN2-55 L3 pmc_connector[70] JN2-57 K6 pmc_connector[71] JN2-58 J19 pmc_connector[72] JN2-60 J20 pmc_connector[73] JN2-61 # This connection goes to PMC_1_pi[4]. K21 pmc_connector[74] JN2-64 # SDRAM connector signals: E16 sdram_ras_n J2-65 C15 sdram_we_n J2-67 C16 sdram_s0_n J2-69 D16 sdram_s1_n J2-71 # Note: sdram_cas_n below is correct. The schematic is incorrect (unless it's been fixed). R12 sdram_cas_n J2-66 T13 sdram_cke0 J2-62 W6 sdram_sda J2-141 W7 sdram_scl J2-142 V13 sdram_dnu J2-73 U13 sdram_ba[1] J2-110 Y14 sdram_ba[0] J2-106 P12 sdram_a[13] J2-72 W14 sdram_a[12] J2-70 V14 sdram_a[11] J2-112 U14 sdram_a[10] J2-111 R13 sdram_a[9] J2-109 Y15 sdram_a[8] J2-105 P7 sdram_dq[63] J2-138 T6 sdram_dq[62] J2-136 Y6 sdram_dq[61] J2-134 Y5 sdram_dq[60] J2-132 AA13 sdram_dq[59] J2-128 AB16 sdram_dq[58] J2-126 AB15 sdram_dq[57] J2-124 AA12 sdram_dq[56] J2-122 AA11 sdram_dq[55] J2-100 AA10 sdram_dq[54] J2-98 AB8 sdram_dq[53] J2-96 AA9 sdram_dq[52] J2-94 AA16 sdram_dq[51] J2-90 AB18 sdram_dq[50] J2-88 AA15 sdram_dq[49] J2-86 AA14 sdram_dq[48] J2-84 AB17 sdram_dq[47] J2-54 AA6 sdram_dq[46] J2-52 AB6 sdram_dq[45] J2-50 AA7 sdram_dq[44] J2-48 AB7 sdram_dq[43] J2-44 AA8 sdram_dq[42] J2-42 AB21 sdram_dq[41] J2-40 AA18 sdram_dq[40] J2-38 AA17 sdram_dq[39] J2-20 AB20 sdram_dq[38] J2-18 AB19 sdram_dq[37] J2-16 AB3 sdram_dq[36] J2-14 AB4 sdram_dq[35] J2-10 AA4 sdram_dq[34] J2-8 AA5 sdram_dq[33] J2-6 AB5 sdram_dq[32] J2-4 # Note: sdram_cke1 below is correct. The schematic is incorrect (unless it's been fixed). Y13 sdram_cke1 J2-68 F16 sdram_dqm[7] J2-118 H16 sdram_dqm[6] J2-116 C17 sdram_dqm[5] J2-26 D17 sdram_dqm[4] J2-24 E17 sdram_dqm[3] J2-117 Y11 sdram_dqm[2] J2-115 T12 sdram_dqm[1] J2-25 Y12 sdram_dqm[0] J2-23 T14 sdram_a[7] J2-104 W15 sdram_a[6] J2-103 Y16 sdram_a[5] J2-34 V15 sdram_a[4] J2-32 W16 sdram_a[3] J2-30 U15 sdram_a[2] J2-33 V16 sdram_a[1] J2-31 U16 sdram_a[0] J2-29 V22 sdram_dq[31] J2-137 V21 sdram_dq[30] J2-135 AA19 sdram_dq[29] J2-133 AA20 sdram_dq[28] J2-131 Y22 sdram_dq[27] J2-127 V2 sdram_dq[26] J2-125 Y1 sdram_dq[25] J2-123 V1 sdram_dq[24] J2-121 AB2 sdram_dq[23] J2-99 W1 sdram_dq[22] J2-97 V20 sdram_dq[21] J2-95 W19 sdram_dq[20] J2-93 Y21 sdram_dq[19] J2-89 W22 sdram_dq[18] J2-87 W21 sdram_dq[17] J2-85 W5 sdram_dq[16] J2-83 Y4 sdram_dq[15] J2-53 Y2 sdram_dq[14] J2-51 W2 sdram_dq[13] J2-49 AA3 sdram_dq[12] J2-47 P16 sdram_dq[11] J2-43 T17 sdram_dq[10] J2-41 Y20 sdram_dq[9] J2-39 R17 sdram_dq[8] J2-37 Y19 sdram_dq[7] J2-19 V3 sdram_dq[6] J2-17 Y3 sdram_dq[5] J2-15 W3 sdram_dq[4] J2-13 V4 sdram_dq[3] J2-9 W4 sdram_dq[2] J2-7 U20 sdram_dq[1] J2-5 V19 sdram_dq[0] J2-3