Faculty & Staff Alex K. JonesAssistant Professor, Department of Electrical and Computer Engineering EducationPh.D. (Computer Engineering), Northwestern University, Evanston, IL, 2002 Selected and Recent PublicationsProfessor Jones' personal web page. A full list of publications is available here (CV). S. Shao, Y. Zhang, A. K. Jones, R. Melhem, "Symbolic Expression Analysis for Compiled Communication," in Proc. of the IEEE IPDPS Workshop on Large Scale Parallel Processing (LSPP), 2008. G. Mehta, C. Ihrig, and A. K. Jones, "Reducing Energy by Exploring Heterogeneity in a Coarse-grain Fabric, in Proc. of the Reconfigurable Architecture Workshop (RAW), 2008. A. K. Jones, S. Dontharaju, S. Tung, L. Mats, P. Hawrylak, R. R. Hoare, J. T. Cain, and M. H. Mickle, "Radio Frequency Identification Prototyping," ACM Transactions on Design Automation for Electronic Systems (TODAES), Vol. 13, No. 2, April, 2008, pp. 1-21, Article 29, DOI 10.1145/1344418.1344425. S. Dontharaju, S. Tung, A. K. Jones, L. Mats, J. Panuski, J. T. Cain, and M. H. Mickle, "The Unwinding of a Protocol," IEEE Communications Magazine - April, 2007.
Research InterestsThere is an alarming trend of improvement in hardware technology with a significant lag in techniques that utilize the technology. Additionally, there is a trend toward mobile devices with increasing capability and longer battery life. In many cases, these trends are in direct conflict. Current state of the art hardware design methodologies for digital systems require the use of hardware description languages and/or tools that make hardware design for complex systems time-consuming, tedious, and error prone. A popular method to use this die-space is to combine several devices that in the past were contained on separate chips into a single chip called a system-on-a-chip (SoC). This technique buys the industry some time and promotes existing IP reuse; however, the real necessity is a generic solution to digital circuit design for deep and very deep sub-micron technology. I am interested in solving the design-automation problem to allow new technology to be efficiently used to create new products. It is possible to abstract this problem by targeting traditional high-level programming languages such as C/C++, MATLAB/SIMULINK, and Java for hardware synthesis. Using high-level languages not only provides a much easier interface to the designer, but also allows the opportunity to attack optimization problems at a variety of different levels to produce a more comprehensive solution. In addition to traditional constraints such as optimization of area and performance, these tools must meet new challenges dictated by technology and industry trends such as power optimization. Toward this end I am interested in developing tools for existing solutions like ASICs and reconfigurable technology such as FPGAs. I am also interested in development of comprehensive solutions for systems that include novel architectures and design tools for high-performance and low-power/mobile applications. |
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