Publications

Refereed Journal Publications

1. S. Shao, Y. Zhang, A. K. Jones, and R. Melhem, Symbolic Expression Analysis for Compiled Communication, Parallel Processing Letters, – in press.

2. R. Hoare, Z. Ding, and A. K. Jones, A Near-optimal Two-stage Hardware Scheduler for Large Cardinality Crossbar Switches, Journal of Parallel and Distributed Computing (JPDC) - in press.

3. A. K. Jones, G. Mehta, J. Stander, M. Baz, and B. Hunsaker, Interconnect Customization for a Hardware Fabric, ACM Transactions on Design Automation for Electronic Systems (TODAES) - in press.

4. S. Dontharaju, S. Tung, J. T. Cain, L. Mats, M. H. Mickle, and A. K. Jones, A Design Automation and Power Estimation Flow for RFID Systems, ACM Transactions on Design Automation for Electronic Systems (TODAES) - in press.

5. S. Shao, A. K. Jones, and R. Melhem, Compiler Techniques for Efficient Communications in Circuit Switched Networks for Multiprocessor Systems, IEEE Transactions for Parallel and Distributed Systems - in press.

6. A. K. Jones, R. A. Walker, Introduction to the Special Issue on Demonstrable Software Systems and Hardware Platforms II, ACM Transactions on Design Automation for Electronics Systems (TODAES), Vol. 13, No. 3, Article 38, July, 2008, DOI 10.1145/1367045.1367047.

7. A. K. Jones, S. Dontharaju, S. Tung, L. Mats, P. Hawrylak, R. R. Hoare, J. T. Cain, and M. H. Mickle, Radio Frequency Identification Prototyping, ACM Transactions on Design Automation for Electronic Systems (TODAES), Vol. 13, No. 2, April, 2008, pp. 1-21, Article 29, DOI 10.1145/1344418.1344425.

8. M. H. Mickle, J. T. Cain, A. K. Jones, Intellectual Property and Ubiquitous RFID, Recent Patents on Electrical Engineering, Vol. 1, No. 1, January 2008, pp. 59-67.

9. A. K. Jones, R. Hoare, S. Dontharaju, S. Tung, R. Sprang, J. Fazekas, J. T. Cain, M. H. Mickle, An Automated, FPGA-based Reconfigurable, Low-Power RFID Tag, Journal of Microprocessors and Microsystems, Vol. 31, No. 2, March 2007, pp. 116-134.

10. S. Dontharaju, S. Tung, A. K. Jones, L. Mats, J. Panuski, J. T. Cain, and M. H. Mickle, The Unwinding of a Protocol, IEEE Applications and Practice - April, 2007, Vol. 1, No. 1, pp. 4-9.

11. A. K. Jones, R. Hoare, D. Kusic, J. Fazekas, G. Mehta, and J. Foster, A VLIW Processor with Hardware Functions: Increasing Performance While Reducing Power, IEEE Transactions on Circuits and Systems II, Vol. 53, No. 11, November 2006, pp. 1250-1254.

12. A. K. Jones, S. Dontharaju, S. Tung, P. Hawrylak, L. Mats, R. Hoare, J. T. Cain, M. H. Mickle, Passive Active Radio Frequency Identification Tags (PART), International Journal of Radio Frequency Identification Technology and Applications (IJRFITA) - Vol. 1, No. 1, 2006, pp. 52-73.

13. J. M. Lucas, R. Hoare, I. S. Kourtev, A. K. Jones, Technology Mapping for Field Programmable Fate Arrays using Content-Addressable Memory (CAM), Journal of Microprocessors and Microsystems - Vol. 30, No. 7, November, 2006, pp. 445-456.

14. A. K. Jones, R. Hoare, D. Kusic, G. Mehta, J. Fazekas, and J. Foster, Reducing Power while Increasing Performance with SuperCISC, ACM Transactions on Embedded Computing Systems (TECS) - Vol. 5, No.3, August 2006, pp. 658-686.

15. J. Schuster, K. Gupta, R. Hoare, and A. K. Jones, Speech Silicon: An FPGA Architecture for Real-time, Hidden Markov Model Based Speech Recognition, EURASIP Journal on Embedded Systems (JES), Vol. 2006, Article ID 48085, 2006, Pages 1-19.

16. G. Mehta, R. R. Hoare, J. Stander, J. Lucas, B. Hunsaker, and A. K. Jones, A Low-Energy Reconfigurable Fabric for the SuperCISC Architecture, Journal of Low Power Electronics (JOLPE) - Vol. 2, No. 2, August 2006, pp. 148-164.

17. P. J. Hawrylak, L. Mats, J. T. Cain, A. K. Jones, S. Tung, M. H. Mickle, Ultra Low-power Computing Systems for Wireless Devices, International Review on Computers and Software (IRECOS), Vol. 1, No. 1, July 2006, pp. 1-10.

18. R. Hoare, A. K. Jones, D. Kusic, J. Fazekas, J. Foster, S. Tung, M. McCloud, Rapid VLIW Processor Customization For Signal Processing Applications Using Combinational Hardware Functions, EURASIP Journal on Applied Signal Processing (JASP), Vol. 2006, Article ID 46473, 2006, pp. 1-23.

19. A. K. Jones, J. Zhang, A. Amer, Entropy Based Evaluation of Communication Predictability in Parallel Applications, IEICE Transactions on Information & Systems, Vol. E89-D, No. 2, February 2006, pp. 469-478.

20. X. Tang, T. Jiang, A. Jones, and P. Banerjee, Behavioral Synthesis with power Estimation and Optimization for Unscheduled Data-Dominated Circuits, Journal of Low Power Electronics, Vol. 1, No.3, December 2005, pp. 259-272.

21. R. Hoare, Z. Ding, S. Tung, Rami Melhem, and A. K. Jones, A Framework for the Design, Synthesis and Cycle-Accurate Simulation of Multiprocessor Networks, Journal of Parallel and Distributed Computing, Vol. 65, No. 10, October 2005, pp. 1237-1252.

22. Y. Yu, R. Hoare, and A. K. Jones, A Unique Hybrid Encoding Scheme for Efficient Range Matching in Ternary Content Addressable Memory, IEE Proceedings on Circuits, Devices & Systems - in revision.

23. Z. Ding, R. Hoare, A. K. Jones, and R. Melhem, Level-wise Scheduling Algorithm for Fat Tree Interconnection Networks, International Journal of Computers and Applications (IJCA) - in review since October 2006.

24. M. Baz, B. Hunsaker, G. Mehta, J. Stander, and A. K. Jones, Mapping and Design of a Hardware Fabric, European Journal of Operations Research (OR) - in review since April 2007, revised March 2008.

25. A. K. Jones, S. Dontharaju, L. Mats, S. Tung, J. T. Cain, P. J. Hawrylak, and M. H. Mickle, Exploring RFID Prototyping in the Virtual Laboratory, IEEE Transactions on Education - in revision

26. A. K. Jones, S. P. Levitan, R. A. Rutenbar, Yuan Xie, Collaborative VLSI-CAD Instruction in the Digital Sandbox, IEEE Transactions on Education - in revision

27. A. K. Jones, Non-uniform “Fat Meshes” for Chip Multiprocessors, Parallel Processing Letters, in review since May 2008.

Chapters in Edited Books

1. C. Ihrig, M. Baz, J. Stander, R. R. Hoare, B. A. Norman, O. Prokopyev, B. Hunsaker, and A. K. Jones, Greedy Algorithms for Mapping onto a Coarse-grained Reconfigurable Fabric, Invited Book Chapter in “Advances in Greedy Algorithms”, V. Kordic, editor, I-Tech Education and Publishing, Vienna, Austria, October 2008.

2. S. Dontharaju, S. Tung, R. R. Hoare, J. T. Cain, A. K. Jones Design Automation for RFID Tags and Systems, Chapter 3 in “RFID Handbook: Applications, Technology, Security, and Privacy,” S. Ahson and M. Ilyas, editors, Taylor and Francis, March 2008.

3. S. Tung, S. Dontharaju, L. Mats, P. J. Hawrylak, J. T. Cain, A. K. Jones, Layers of Security for Active RFID Tags, Chapter 33 in “RFID Handbook: Applications, Technology, Security, and Privacy.” S. Ahson and M. Ilyas, editors, Taylor and Francis, March 2008.

4. A. K. Jones, S. Tung, S. Dontharaju, P. J. Hawrylak, L. Mats, J. T. Cain, Minimum Energy/Power Considerations, Chapter 11 in “RFID Handbook: Applications, Technology, Security, and Privacy.” S. Ahson and M. Ilyas, editors, Taylor and Francis, March 2008.

5. A. Jones, D. Bagchi, S. Pal, P. Banerjee, A. Choudhary. A Compiler with Power and Performance Optimizations, appears in “Power Aware Computing,” R. Graybill, R. Melhem, editors, Kluwer Academic Publishers, 2002.

Refereed Conference Proceedings (full papers)

1. S. Shao, Y. Zhang, A. K. Jones, R. Melhem, Symbolic Expression Analysis for Compiled Communication, IEEE Workshop on Large Scale Parallel Processing (LSPP), 2008, pp. 286.1 - 286.8.

2. S. Tung and A. K. Jones, Physical Layer Design Automation for RFID Systems, Reconfigurable Architecture Workshop (RAW), 2008, pp. 117.1 - 117.8.

3. G. Mehta, C. Ihrig, and A. K. Jones, Reducing Energy by Exploring Heterogeneity in a Coarse-grain Fabric, Reconfigurable Architecture Workshop (RAW), 2008, pp. 104.1 - 104.8.

4. Y. Yu, R. R. Hoare, and A. K. Jones, A CAM-based Intrusion Detection System for Single-packet Attack Detection, Reconfigurable Architecture Workshop (RAW), 2008, pp. 119.1 - 119.8.

5. A. K. Jones, S. R. Dontharaju, L. Mats, James T. Cain, and M. H. Mickle, Exploring RFID Prototyping in the Virtual Laboratory, MSE Conference, 2007, pp. 137-138.

6. A. K. Jones, S. Levitan, R. A. Rutenbar, and Y. Xie, Collaborative VLSI-CAD Instruction in the Digital Sandbox, MSE Conference, 2007, pp. 141-142.

7. A. K. Jones, R. R. Hoare, J. St. Onge, J. Lucas, S. Shao, and R. Melhem, Linking Compilation and Visualization for Massively Parallel Programs, IPDPS/APDCM Workshop, pp. 228.1 - 228.8, 2007.

8. C. J. Ihrig, J. Stander, and A. K. Jones, Pipelining Tradeoffs of Massively Parallel SuperCISC Hardware Functions, IPDPS/APDCM Workshop, pp. 227.1 - 227.8, 2007.

9. G. Mehta, J. Stander, M. Baz, B. Hunsaker, A. K. Jones, Interconnect Customization for a Coarse-grained Reconfigurable Fabric, IPDPS Reconfigurable Architecture Workshop (RAW), pp. 165.1 - 165.8, 2007.

10. Z. Ding, R. Hoare, A. K. Jones, R. Melhem, Level-wise Scheduling Algorithm for Fat Tree Interconnection Networks, Proc. of Supercomputing (SC), 2006, pp. 165.1 - 165.9.

11. R. Hoare, Z. Ding, A. K. Jones, A Near-optimal Real-time Hardware Scheduler for Large Cardinality Crossbar Switches, Proc. of Supercomputing (SC), 2006, pp. 164.1 - 164.12.

12. A. K. Jones, R. Hoare, S. R. Dontharaju, S. Tung, R. Sprang, J. Fazekas, J. T. Cain, and M. H. Mickle, A Field Programmable RFID Tag and Associated Design Flow, Proc. of the IEEE Symposium on Field Programmable and Custom Computing Machines (FCCM), 2006, pp. 165-174.

13. S. Shao, A. K. Jones, R. Melhem, A Compiler-based Communication Analysis Approach for Multiprocessor Systems, Proc. of IEEE/ACM International Parallel and Distributed Processing Symposium (IPDPS), 2006, DOI: 10.1109/IPDPS.2006.1639322, 10 pages.

14. Y. Yu, R. Hoare, A. K. Jones, R. Sprang, A Hybrid Encoding Scheme that Enables Single-cycle Range Matching in Content Addressable Memory, Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), 2006, pp. 791-794.

15. A. K. Jones, R. Hoare, S. Dontharaju, S. Tung, R. Sprang, J. Fazekas, J. T. Cain, M. H. Mickle, An Automated, FPGA-based Reconfigurable, Low-Power RFID Tag, Proc. of IEEE/ACM Design Automation Conference (DAC), 2006, pp. 131-136.

16. R. Hoare, A. K. Jones, D. Kusic, J. Fazekas, G. Mehta, and J. Foster, A VLIW Processor with Hardware Functions: Increasing Performance While Reducing Power, Proc. of HPEC, September 2005, pp. 5-6.

17. K. J. Barker, A. Benner, R. Hoare, A. Hoisie, A. K. Jones, D. J. Kerbyson, D. Li, R. Melhem, R. Rajamony, E. Schenfeld, S. Shao, C. Stunkel, and P. A. Walker, On the Feasibility of Optical Circuit Switching for High Performance Computing Systems, IEEE/ACM Supercomputing Conference (SC), 2005, pp. 16-1 – 16-22.

18. D. Kusic, R. Hoare, A. K. Jones, J. Fazekas, J. Foster, Extracting Speedup from C-code with Poor Instruction-level Parallelism, Workshop of Massively Parallel Processing (WMPP), 2005, pp. 264-9 - 264-18.

19. A. K. Jones, R. Hoare, D. Kusic, J. Fazekas, and J. Foster, An FPGA-based VLIW Processor with Custom Hardware Execution, ACM International Symposium on Field-Programmable Gate Arrays (FPGA) 2005, pp. 107-117.

20. R. Melhem, R. Hoare, A. Jones, Z. Ding, S. Tung, D. Li, S. Shao, J. Zheng, Enabling Predictive Multiplexed Switching in Multiprocessor Networks, International Parallel & Distributed Processing Symposium, 2005, pp. 100-1 - 100-10.

21. X. Tang, T. Jiang, A. Jones, P. Banerjee, Behavioral Synthesis of Data Dominated Circuits for Minimal Energy Implementation, IEEE International Conference on VLSI Design, Taj Bengal, Kolkata, India, January 2005, pp. 267-273.

22. J. Lucas, R. Hoare, I. Kourtev, A. Jones, LURU: Global Scope FPGA Technology Mapping with Content-Addressable Memories, International Conference on Electronics, Circuits, and Systems (ICECS), Tel Aviv, Isreal, December, 2004, pp. 599-602.

23. A. Jones, R. Hoare, I. Kourtev, J. Fazekas, D. Kusic, J. Foster, S. Boddie, A. Muaydh, A 64-way VLIW/SIMD FPGA Processing Architecture and Design Flow. International Conference on Electronics, Circuits, and Systems (ICECS), Tel Aviv, Israel, December, 2004, pp. 499-502.

24. B. Brady, A. Jones, I. Kourtev, Efficient CAD Development for Emerging Technologies using Objective-C and Cocoa, International Conference on Electronics, Circuits, and Systems (ICECS), Tel Aviv, Israel, December 2004, pp. 369-372.

25. A. Jones, X. Tang, P. Banerjee, Compile-time Simulation for Low-Power Optimization using SystemC, Modelling and Simulation Conference, Marina Del Ray, CA, 2004, pp. 78-83.

26. T. Jiang, X. Tang, A. Jones, P. Banerjee, Optimizing Power While Exploiting Fine Grain Parallelism on FPGAs, IASTED International Conference on Parallel and Distributed Computing and Systems (PDCS), November 2003, pp. 357-362.

27. R. Mukherjee, A. Jones, P. Banerjee, System Level Synthesis of Multiple IP Blocks in the Behavioral Synthesis Tool, International Conference on Parallel and Distributed Computing and Systems (PDCS), November 2003, pp.363-368. Best Paper Award Nominee

28. X. Tang, T. Jiang, A. Jones, P. Banerjee, Compiler Optimizations in the PACT HDL Behavioral Synthesis Tool for ASICs and FPGAs, IEEE International SoC Conference (SoC), September 2003, pp. 189-192.

29. A. Jones, D. Bagchi, S. Pal, X. Tang, A. Choudhary, P. Banerjee, PACT HDL: A C Compiler with Power and Performance Optimizations, International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), Grenoble, France, October 2002, pp. 188-197.

30. A. Jones, A. Nayak, P. Banerjee. Parallel Implementation of Matrix and Signal Processing Libraries on FPGAs, International Conference on Parallel and Distributed Computing and Systems (PDCS), Anaheim, CA, August 2001, pp. 370-377. Best Paper Award Nominee

31. P. Banerjee, N. Shenoy, A. Choudhary, S. Hauck, C. Bachmann, M. Chang, M. Haldar, P. Joisha, A. Jones, A. Kanhare, A. Nayak, S. Periyacheri, M. Walkden, MATCH: A MATLAB Compilation Environment for Configurable Computing Systems, International Symposium on Field-Programmable Custom Computing Machines (FCCM), Napa, CA, 2000, pp. 39-48.

32. S. Periyacheri, A. Jones, A. Nayak, D. Zaretsky, P. Banerjee, N. Shenoy, A. Choudhary. Library Functions in Reconfigurable Hardware for Matrix and Signal Processing Operations in MATLAB, International Conference on Parallel and Distributed Computing and Systems (PDCS 1999), Cambridge, MA, November, 1999.

Refereed Conference Proceedings (extended abstracts)

1. J. Lucas, R. Hoare, I. Kourtev, and A. K. Jones, Technology Mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM), Proc. of the IEEE Symposium on Field Programmable and Custom Computing Machines (FCCM), 2006, pp. 299-300.

2. G. Mehta, R. Hoare, J. Stander, A. K. Jones, A Low-Energy Reconfigurable Fabric for the SuperCISC Architecture, Proc. of the IEEE Symposium on Field Programmable and Custom Computing Machines (FCCM), pp. 309-310.

3. G. Mehta, R. Hoare, J. Stander, A. Jones, Design Space Exploration for Low-Power Reconfigurable Fabrics, Proc. of IEEE/ACM Reconfigurable Architectures Workshop (RAW), 2006.

4. R. Hoare, A. K. Jones, D. Kusic, J. Fazekas, G. Mehta, and J. Foster, A VLIW Processor with Hardware Functions: Increasing Performance While Reducing Power, Proc. of the Workshop on High Performance Embedded Computing (HPEC’05).

5. J. Lucas, R. Hoare, I. Kourtev, and A. K. Jones, LURU2: Optimizing Technology Mapping for FPGAs Using CAMs, IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), 2005, pp. 293-294.

6. R. Mukherjee, A. Jones, P. Banerjee, Handling Data Streams while Compiling C Programs onto Hardware, International Symposium on VLSI (ISVLSI), Lafayette, Louisiana, February, 2004, pp. 271-272.

7. A. Jones, P. Banerjee, An Automated and Power-Aware Framework for Utilization of IP Cores in Hardware Generated from C Descriptions Targeting FPGAs, IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), Napa, CA, 2003, pp.284-285.

8. A. Jones, P. Banerjee, An Automated and Power-Aware Framework for Utilization of IP Cores in Hardware Generated from C Descriptions Targeting FPGAs, ACM International Symposium on Field-Programmable Gate Arrays (FPGA), Monterey, California, February, 2003, pp. 244.

Publications - Alex K. Jones