Alex K. Jones
Assistant Professor
Department of Electrical and Computer Engineering
Department of Computer Science (Secondary)
Computer Engineering Program
University of Pittsburgh
334 Benedum Hall
(412) 624-9666
(412) 624-8003 (fax)
 
 
Academics and Research
To effectively solve current and future computing problems it is not enough to develop new architectures or design automation tools. The solution must take a "top to bottom" approach finding new architectures, design tools, and even fabrication techniques to develop complete systems.

Education
  1.  Ph.D. in Electrical and Computer Engineering
     Northwestern University, 2002.
  1.  M.Sc. in Electrical and Computer Engineering
     Northwestern University, 2000.
  1.  B.Sc. in Physics, College of William and Mary, 1998.
 
Current CV [ ps | pdf ]
 
Teaching
ECE 2140:         System-on-a-Chip Design
ECE 2120:         Hardware Design Methodologies
ECE.CoE 0132: Digital System Design
ECE/CoE 0501: Digital Laboratory
ECE 2130:         VLSI CAD
 
Students
Gayatri Mehta, Ph.D. Candidate
Shenchih Tung, Ph.D. Candidate
Shuyi Shao, Ph.D. Candidate - co-advised with Rami Melhem
Colin Ihrig, M.Sc. Student
Gerold Joseph Dhanabalan, M.Sc. Student
Yu Zhang, M.Sc. Student
 
Selected and Recent Publications
 
 
  1.  A. K. Jones, S. Dontharaju, S. Tung, L. Mats, P. J. Hawrylak, R. R. Hoare, J. T. Cain, M. H. Mickle, “Radio Frequency Identification Prototyping,” ACM Transactions on Design Automation for Electronic Systems, in press.
 
  1.  A. K. Jones, R. Hoare, S. Dontharaju, S. Tung, R. Sprang, J. Fazekas, J. T. Cain, M. H. Mickle, “An Automated, FPGA-based Reconfigurable, Low-Power RFID Tag”, Journal of Microprocessors and Microsystems, Vol. 31, No. 2, March 2007, pp. 116-134.
 
  1.  S. Dontharaju, S. Tung, A. K. Jones, L. Mats, J. Panuski, J. T. Cain, and M. H. Mickle, “The Unwinding of a Protocol,” IEEE Communications Magazine - April, 2007.
 
  1.  A. K. Jones, R. Hoare, D. Kusic, J. Fazekas, G. Mehta, and J. Foster, “A VLIW Processor with Hardware Functions: Increasing Performance While Reducing Power,” IEEE Transactions on Circuits and Systems II, Vol. 53, No. 11, November 2006, pp. 1250-1254.
 
  1.   J. M. Lucas, R. Hoare, I. S. Kourtev, A. K. Jones, “Technology Mapping for Field Programmable Fate Arrays using Content-Addressable Memory (CAM),” Journal of Microprocessors and Microsystems - Vol. 30, No. 7, November, 2006, pp. 445-456.
 
  1.  A. K. Jones, R. Hoare, D. Kusic, G. Mehta, J. Fazekas, and J. Foster, “Reducing Power while Increasing Performance with SuperCISC,” ACM Transactions on Embedded Computing Systems (TECS) - Vol. 5, No.3, August 2006, pp. 658-686.
 
  1.  Z. Ding, R. Hoare, A. K. Jones, R. Melhem, “Level-wise Scheduling Algorithm for Fat Tree Interconnection Networks,” Proceedings of Supercomputing (SC), 2006.
 
  1.  R. Hoare, Z. Ding, A. K. Jones, “An Area and Time Optimized Hardware Scheduler for Optimal Crossbar Scheduling in Real-time,” Proceedings of Supercomputing (SC), 2006.
 
  1.  A. K. Jones, R. Hoare, S. Dontharaju, S. Tung, R. Sprang, J. Fazekas, J. T. Cain, M. H. Mickle, “An Automated, FPGA-based Reconfigurable, Low-Power RFID Tag,” Proceedings of IEEE/ACM Design Automation Conference (DAC), 2006.