About Us ABET ECE 1193/2193Advanced VLSI Design Project(3 credits) Description: The 1193 course is organized as a full semester-long project. Students team-up in small groups (about four to six students depending on enrollment) which design and implement different VLSI projects of moderate to high complexity. These projects are of significant difficulty requiring an in-depth understanding and analysis of various directions of the design space. Students explore their design assignments within various levels of abstraction, starting at the specifications and architecture levels and going all the way down to the physical level. At the conclusion of the course, completed and simulated student designs are submitted for fabrication by the NSF MOSIS (MOS Implementation Service) academic program or through a participating academic partner. Starting in the 2002/2003 academic year, this course has been taught on a collaborative basis–as a part of the Digital Sandbox Initiative–with Carnegie Mellon University and The Pennsylvania State University as the other two participating institutions. An audio-visual infrastructure is in place to enable simultaneous attendance of lectures by students at all three universities–the lecture is delivered from a single source and observed at all participating institutions. Several times throughout the semester, the students also participate in multi-sites design reviews. Students deliver periodic updates on their progress to a three-university audience that acts as an additional motivator for high performance in this advanced course. The circuit implementation is realized in a standard CMOS process. All high-level descriptions are designed, simulated, and synthesized using the Verilog Hardware Description Language. Silicon Assembly is accomplished using Cadence’s SOC Encounter. Verification is accomplished using assertions and (in some cases) the e-language. Prerequisites : ECE/COE 1192, senior or graduate status. Required Texts : (1) J. Uyemura, Introduction to VLSI Circuits and Systems, John Wiley and Sons, Inc., 2001. Additional Texts: (1) N. Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective, Third Edition, Addison Wesley, 2004. (2) S. Palnitkar, Verilog HDL: A Guide to Digital Design and Synthesis, Second Edition, Prentice-Hall, Inc., 2003. (3) S. Palnitkar, Design Verification with e, Prentice-Hall, Inc., 2002.. (4) I. Sutherland, B. Sproull, and D. Harris, Logical Effort: Designing Fast CMOS Circuits, Morgan Kaufmann Publishers, 1999. (5) Professional literature such as the IEEE Transactions on Computers, on VLSI Systems, on Computer-Aided Design, and on Circuits and Systems, as well as the IEEE Journal of Solid-State Circuits. Course Objectives : To strengthen understanding and practice of fundamental principles underlying digital design using a modern CMOS ASIC semiconductor design process. To deepen the understanding and appreciation of all issues involved in the modeling, simulation, and physical design of ASIC CMOS circuits and to improve effective use of a variety of complex Computer-Aided Design (CAD) tools. To strengthen problem-solving and team-working skills in order to successfully tackle a digital design project of high complexity. Topics Covered : Introduction and motivation, in-depth description of the ASIC design flow and the CAD Tools used in this design flow. Silicon boot camp: an intense one-month period of Verilog HDL from concept to synthesis. Structured Verilog design and principles of hierarchy, improve understanding and description of concurrency in hardware, practice writing synthesizable Verilog HDL descriptions. Learn and practice various verification approaches such as assertion-based verification. Optional coverage of the e-language. Architectural design specifications and discussion. Examples of past projects include a network-on-a-chip based Low Density Parity Check (LDPC) decoder and a low power, speech-recognition on-a-chip design. Design specification at the architecture level, developing a verification framework, synthesis, Silicon assembly. Multiple periodic progress updates and a final presentation and design document. Class/Laboratory Schedule : The lecture for this course typically meets twice a week for 1 hr, 15 min. In addition, a 1 hour/week laboratory session is used to demonstrate the software CAD tools. Considerable additional unscheduled laboratory time is required and made available to the students in this course in our dedicated VLSI CAD and Design Automation Lab in Benedum Hall 370. Professional Component Contributions : An open ended design projects with high-level specification and multiple solution paths. Group project. Written and oral presentation skills. Use of state-of-the-art Engineering tools (computers and software). Prepared by: Ivan S. Kourtev Date Prepared: May 2005
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