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About Us ABET ECE 1192/2192

Introduction to VLSI Design

(4 credits)

Description: 1192 is an introductory to intermediate level course in digital integrated circuit design with emphasis on developing understanding and intuition at all levels from physical through architecture. The course contains an overview of the principles of both MOSFET's and BJT's and focuses on various design styles for digital circuits such as static/dynamic/domino CMOS. Other circuit design styles such as BiCMOS and ECL circuits are analyzed briefly. Both combinational and sequential circuits are discussed, and the performance characteristics and tradeoffs of these circuits are analyzed. Circuit simulation techniques–specifically, the circuit simulator hspice–are extensively used. On a higher level of abstraction, there is exposure to the Verilog Hardware Description Language and simulation with Verilog using simple to moderate examples. Other CAD tools for circuit physical design and simulation are used.

Prerequisites : ECE/COE 0142 or COE/CS 0447, Computer Organization, senior status.

Required Texts : (1) J. Uyemura, Introduction to VLSI Circuits and Systems, John Wiley and Sons, Inc., 2001. (2) I. Sutherland, B. Sproull, and D. Harris, Logical Effort: Designing Fast CMOS Circuits, Morgan Kaufmann Publishers, 1999.

Additional Texts: (1) N. Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective, Third Edition, Addison Wesley, 2004. (2) S. Palnitkar, Verilog HDL: A Guide to Digital Design and Synthesis, Second Edition, Prentice-Hall, Inc., 2003. (3) Professional literature such as the IEEE Transactions on Computers, on VLSI Systems, on Computer-Aided Design, and on Circuits and Systems, as well as the IEEE Journal of Solid-State Circuits.

Course Objectives :

  • To develop a formal understanding of the operation of devices and to gain an intuitive insight into the semiconductor industry evolution and trends.
  • To learn fundamental principles underlying digital design using semiconductor devices and to understand the performance characteristics of these digital circuits.
  • To develop an appreciation of the issues involved in the modeling, simulation, and physical design of digital semiconductor circuits and to understand how to effectively use a variety of Computer-Aided Design (CAD) tools.
  • To develop problem-solving skills in order to be able to successfully approach a digital design project of medium to high complexity in the second semester (1193).

    • Topics Covered : Introduction and motivation, UNIX/X-windows/text editors, VLSI design process, simple CMOS from concept to logic and circuits, Verilog HDL description and documentation of designs, hspice simulation, Cadence Vrtuoso tutorials and physical design. Details of the MOS transistor, CMOS fabrication process, CMOS inverter. Second-order effects in the CMOS inverter and more complex CMOS circuits, electrical and physical design rules, parasitic impedances, performance characteristics, power dissipation, and scaling issues. Standard CMOS logic gates, system timing, performance optimization through circuit sizing. Transmission gate design styles, and generalized procedures for designing transmission gates based circuits for arbitrary functions. I/O’s and pad structures. System timing revisited, microarchitecture issues, introduction to sequential circuit design. Dynamic MOS circuit design style and its advantages and flaws. Race-free dynamic styles, such as domino dynamic circuits, bubble-pushing procedures, and domino circuits problems based on the lack of inversion. System issues such as system-wide simulation, testing, packaging and ESD protection. System clocking and timing issues, design of the clock distribution network. Scan-design for testing. Test generation and fault analysis. Performance optimization of MOS-based circuits–the method of Logical Effort. Mathematical foundations and derivation of the method. Application on a variety of circuits–from single gates to more complex datapath structures. Design examples. A moderate complexity project to be planned, designed, simulated, and debugged in approximately 4-6 weeks.  

    Class/Laboratory Schedule : The lecture for this course typically meets twice a week for 1 hr, 15 min. In addition, a 1 hour/week laboratory session is used to demonstrate the software CAD tools. Considerable additional unscheduled laboratory time is required and made available to the students in this course in our dedicated VLSI CAD and Design Automation Lab in Benedum Hall 370.

    Professional Component Contributions : Open ended design projects with multiple solution paths. Group projects. Written presentation skills. Use of state-of-the-art Engineering tools (computers and software).

    Prepared by: Ivan S. Kourtev

    Date Prepared: May 2005

     

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