About Us ABET ECE/COE 0142Computer Organization(3 credits) Description: Digital computer data representation, instruction formats, control, memory and input-output units associated with microprocessors, microcontrollers and other digital systems. Prerequisites: ECE/COE 0132 Digital Logic. Text: Computer Systems Design and Architecture, Vincent P. Heuring and Harry F. Jordan, Pearson/Prentice Hall, Second Edition, 2004. Course Objectives: The objectives of the course include providing the students with a foundation in digital information representation and CPU design concepts including data path design, ALU design and control unit design. Memory and I/O subsystems design and their interface with the CPU are also course objectives as well as is experience in Assembly Language programming. Topics Covered: Review of functional decomposition of a computer, the control part vs. the data path – register file vs. functional unit – need for information representation. Information representation; – exponent powers of 2, 8 and 16, binary coded numeric data, fixed point – sign-magnitude, radix complement, radix minus one’s complement – binary point reference and the IEEE Standard 754-1985 for Floating-Point numbers. Decimal and alphanumeric codes BCD and ASCII; binary fixed point arithmetic, addition and subtraction – 2’s complement and 1’s complement, along with multiplication/division algorithms and ALU design. Classifying computers by their instructions and means of accessing memory. Accumulator, stack and general register machines. Instruction formats, addressing modes and instruction types. The instruction fetch-execute cycle including effective address calculations and accessing operands from registers & memory. Complex and Reduced Instruction Set Computer systems: an historical perspective along with driving factors/motivations, contrasts and similarities. Abstract Register Transfer Notational definition for a specific Instruction Set Architecture, the SRC – Simple RISC Computer. SRC provides the primary platform and frame of reference for CPU design topics and Assembly Language programming topics. These concepts also provide a basis for study of the real-world ISAs, MC68000 and SPARC covered in the text and through homework assignments and recitation problems. Use of tri-state buffers and the associated gate and strobe control signals required for register/data transfers using buses. Concrete RTN and control signal sequences describing the various means of implementing the SRC ISA based on 1, 2 & 3 CPU-bus microarchitectures. Control Unit design, hardwired vs. microprogrammed. Machine reset and exception handling. The encoding of instructions: machine code vs. Assembly Language instructions how they relate to one another; SRC simulator and assembler – source, listing and binary files, and Assembly Language programming. Instruction count, clocks per instruction, execution time, measuring of performance and price/performance tradeoffs. Concepts related to performance enhancement; – instruction overlap, prefetching, superscalar operation and pipelining. Memory; – RAM its physical/logical organization along with the concepts of memory hierarchy and cache. I/O Unit; – memory mapped vs. ported I/O, sample peripherals, interrupts, DMA and error checking. I/O interface, serial communication and modes of transfer. Class/Laboratory Schedule: Class meets twice per week in 75-minute lecture sessions and a single 50-minute recitation session. Professional Component Contributions: This required course contributes to the one and one-half years of engineering science and design topics. Students are encouraged to work in groups for homework and software design projects but are required to individually submit neat, well-organized assignment solutions. Students are assigned several SRC Assembly Language programs to develop, assemble, and simulate. Prepared6/28/05ared: March 8, 2005
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